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BGS15MA12 sp5t rx diversity switch data sheet revision 3.1 - 2016-05-11 power management & multimarket
edition 2016-05-11 published by in?neon technologies ag 81726 munich, germany c 2016 in?neon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, in?neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest in?neon technologies of?ce ( www.in?neon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest in?neon technologies of?ce. in?neon technologies components may be used in life-support devices or systems only with the express written approval of in?neon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
BGS15MA12 revision history document no.: BGS15MA12__v3.1.pdf revision history: rev. v3.1 previous version: revision v3.0 - 2015-07-24 page subjects (major changes since last revision) 20 carrier tape drawing updated (fig. 12) trademarks of in?neon technologies ag hvic tm , ipm tm , pfc tm , au-convertir tm , aurix tm , c166 tm , canpak tm , cipos tm , cipurse tm , cooldp tm , coolgan tm , coolir tm , coolmos tm , coolset tm , coolsic tm , dave tm , di-pol tm , directfet tm , drblade tm , easypim tm , econobridge tm , econodual tm , econopack tm , econopim tm , eicedriver tm , eupec tm , fcos tm , ganpowir tm , hexfet tm , hitfet tm , hybridpack tm , imotion tm , iram tm , isoface tm , isopack tm , ledrivir tm , litix tm , mipaq tm , modstack tm , my-d tm , novalithic tm , optiga tm , optimos tm , origa tm , powiraudio tm , powirstage tm , primepack tm , primestack tm , profet tm , pro-sil tm , rasic tm , real3 tm , smartlewis tm , solid flash tm , spoc tm , strongirfet tm , supirbuck tm , tempfet tm , trenchstop tm , tricore tm , uhvic tm , xhp tm , xmc tm . other trademarks all referenced product or service names and trademarks are the property of their respective owners. trademarks updated november 2015 data sheet 3 revision 3.1 - 2016-05-11
BGS15MA12 contents 1 features 5 2 product description 5 3 maximum ratings 6 4 operation ranges 8 5 rf characteristics 9 6 mipi rffe speci?cation 11 7 application information 17 8 package information 19 list of figures 1 BGS15MA12 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 mipi to rf time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 power-up settling time de?nition: a) when the device is already in active mode. b) when changing from low power mode to active mode. after power-up of vio the device is set to low power mode. an additional mipi instruction is necessary to set the switch to active mode. this case is covered by b) . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 received clock signal constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 bus active data receiver timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 bus park cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 bus active data transmission timing speci?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 requirements for vio-initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 BGS15MA12 pin con?guration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 BGS15MA12 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11 atslp-12-4 package outline (top, side and bottom views) . . . . . . . . . . . . . . . . . . . . . . . . . 19 12 marking speci?cation (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13 footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14 atslp-12-4 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 list of tables 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 maximum ratings, table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 maximum ratings, table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 operation ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 rf input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 rf characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 mipi features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 mipi rffe operating timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11 truth table, register_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12 pin de?nition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 data sheet 4 revision 3.1 - 2016-05-11
BGS15MA12 BGS15MA12 sp5t rx diversity switch 1 features low insertion loss low harmonic generation high port-to-port-isolation suitable for lte / wcdma rx applications 0.1 to 2.9 ghz coverage no decoupling capacitors required if no dc applied on rf lines on chip control logic including esd protection integrated mipi rffe interface operating in 1.1 to 1.95 v voltage range software programmable mipi rffe usid direct to battery supply small form factor 1.1 mm x 1.9 mm no power supply blocking required high emi robustness rohs and weee compliant package 2 product description the BGS15MA12 rf mos switch is speci?cally designed for lte and wcdma diversity applications. this sp5t offers low insertion loss and low harmonic generation in termination mode. the switch is controlled via a mipi rffe controller. the on-chip controller allows power-supply voltages from 1.1 to 1.95 v. the switch features direct-connect-to-battery functionality and dc-free rf ports. unlike gaas tech- nology, external dc blocking capacitors at the rf ports are only required if dc voltage is applied externally. the BGS15MA12 rf switch is manufactured in in?neons patented mos technology, offering the performance of gaas with the economy and integration of conventional cmos including the inherent higher esd robustness. the device has a very small size of only 1.1 x 1.9 mm 2 and a maximum height of 0.65 mm. table 1: ordering information type package marking chip BGS15MA12 atslp-12-4 s4 m4829 data sheet 5 revision 3.1 - 2016-05-11
BGS15MA12 figure 1: BGS15MA12 block diagram 3 maximum ratings table 2: maximum ratings, table i at t a = 25 c, unless otherwise speci?ed parameter symbol values unit note / test condition min. typ. max. frequency range f 0.1 C C ghz 1) supply voltage v bat -0.5 C 6.0 v C storage temperature range t stg -55 C 150 c C junction temperature t j C C 125 c C rf input power at all rx ports p rf_rx C C 27 dbm cw esd capability, cdm 2) v esd_cdm -1 C +1 v all pins esd capability, hbm 3) v esd_hbm -1 C +1 kv digital, digital versus rf -1 C +1 kv rf 1) there is also a dc connection between switched paths. the dc voltage at rf ports v rfdc has to be 0v. 2) field-induced charged-device model jesd22-c101. simulates charging/discharging events that occur in production equipment and processes. potential for cdm esd events occurs whenever there is metal-to-metal contact in manufacturing. 3) human body model ansi/esda/jedec js-001-2012 (r=1.5 k
, c=100 pf). 4) iec 61000-4-2 (r=330
, c=150 pf), contact discharge. data sheet 6 revision 3.1 - 2016-05-11 o
BGS15MA12 table 3: maximum ratings, table ii at t a = 25 c, unless otherwise speci?ed parameter symbol values unit note / test condition min. typ. max. maximum dc-voltage on rf- ports and rf-ground v rfdc 0 C 0 v no dc voltages allowed on rf-ports rffe supply voltage v io -0.5 C 3 v C rffe control voltage lev- els at sclk, sdata, ssel1, ssel2 v -0.7 C v io +0.7 (max. 3) v C data sheet 7 revision 3.1 - 2016-05-11
BGS15MA12 4 operation ranges table 4: operation ranges parameter symbol values unit note / test condition min. typ. max. supply voltage v bat 2.2 C 5.5 v C supply current 3) i bat C 80 200 a C supply current in standby mode 3) i bat_sb C 0.5 1 a vio=low or mipi low-power mode rffe supply voltage v io 1.1 1.8 1.95 v C rffe input high voltage 1) v ih 0.7*v io C v io v C rffe input low voltage 1) v il 0 C 0.3*v io v C rffe output high voltage 2) v oh 0.8*v io C v io v C rffe output low voltage 2) v ol 0 C 0.2*v io v C rffe control input capaci- tance c ctrl C C 2 pf C rffe supply current i vio C 15 C a idle state ambient temperature t a -30 25 85 c C 1) sclk, sdata, ssel1 and ssel2 2) sdata 3) t a = ?30 c - 85 c, v bat = 2.2 - 5.5 v table 5: rf input power parameter symbol values unit note / test condition min. typ. max. rx ports (50
) p rf_rx C C 24 dbm C data sheet 8 revision 3.1 - 2016-05-11
BGS15MA12 5 rf characteristics table 6: rf characteristics at t a = ?30 cC85 c, p in = 0 dbm, supply voltage v bat = 2.2 vC5.5 v, unless otherwise speci?ed parameter symbol values unit note / test condition min. typ. max. insertion loss 1) all rx ports il 0.2 0.28 0.35 db 700C1000 mhz 0.25 0.35 0.5 db 1700C2200 mhz 0.3 0.42 0.6 db 2300C2700 mhz return loss 1) all rx ports rl 20 30 C db 700C1000 mhz 18 28 C db 1700C2200 mhz 12 22 C db 2300C2700 mhz isolation all rx ports iso 24 34 C db 700C1000 mhz 17 27 C db 1700C2200 mhz 15 25 C db 2300C2700 mhz isolation rx ports to ai iso 26 36 C db 700C1000 mhz 21 31 C db 1700C2200 mhz 18 28 C db 2300C2700 mhz p1 db compression point, extrapolated all rx ports p 1db >30 C C dbm harmonic generation up to 12.75 ghz all rx ports p harm C -95 -75 dbc 20 dbm, 50
, cw mode intermodulation distortion in rx band 2) (t a = 25 c, v bat = 2.6 v) imd2, low imd2 low C -115 -105 dbm tx = 10 dbm, interferer = ?15 dbm, 50
imd3 imd3 C -125 -110 dbm imd2, high imd2 high C -120 -110 dbm switching time rf rise time rx port on/off t on/off 0.5 1 5 s 90 % off to 90 % on; 90 % on to 90 % off mipi to rf time t int 0.5 1.5 5 s 50 % last sclk falling ?ank to 90 % on, fig. 2 power up settling time t pus C 10 25 s after power down mode, fig. 3 1) on application board with a rf low-q two element matching network at the antenna port 2) on application board with shunt inductor, min/max-values measured with phase shifter. data sheet 9 revision 3.1 - 2016-05-11
BGS15MA12 figure 2: mipi to rf time figure 3: power-up settling time de?nition: a) when the device is already in active mode. b) when changing from low power mode to active mode. after power-up of vio the device is set to low power mode. an additional mipi instruction is necessary to set the switch to active mode. this case is covered by b) . data sheet 10 revision 3.1 - 2016-05-11 90% sclk rf signal sd a t a t int sclk sd a t a t pup vio vb a t b) sclk sd a t a t pup vio vb a t a)
BGS15MA12 6 mipi rffe speci?cation all sequences are implemented according to the mipi alliance speci?cation for rf front-end control interface document version 1.10 - 26. july 2011. table 7: mipi features feature supported comment register write command sequence yes register read command sequence yes extended register write command sequence no up to 4 bytes extented register read command sequence no up to 4 bytes register 0 write command sequence yes trigger function yes trigger assignment to each control register is sup- ported programmable usid yes 3 register command sequence and extended regis- ter command sequence status register yes register for debugging reset yes by vio, power mode and rffe_status group sid yes ssel1 and ssel2 pins yes external pins for changing usid: ssel1=0 & ssel2=0 ! 1000, ssel1=0 & ssel2=1 ! 1001, ssel1=1 & ssel2=0 ! 1010, ssel1=1 & ssel2=1 ! 1011 full speed write yes half speed read yes full speed read yes table 8: startup behavior feature state comment power status low power the chip is in low power mode after startup trigger function enabled trigger function is enabled after startup. trigger function can be dis- abled via pm_trig register. data sheet 11 revision 3.1 - 2016-05-11
BGS15MA12 table 9: mipi rffe operating timing parameter symbol values unit note / test condition min. typ. max. sclk frequency fsclk 0.032 C 26 mhz full speed 0.032 C 13 mhz half speed sclk period tsclk 0.038 C 32 s full speed 0.077 C 32 s half speed sclk low period tsclkil 11.25 C C ns full speed, see fig. 4 24 C C ns half speed, see fig. 4 sclk high period tsclkih 11.25 C C ns full speed, see fig. 4 24 C C ns half speed, see fig. 4 sdata setup time ts 1 C C ns full speed, see fig. 5 2 C C ns half speed, see fig. 5 sdata hold time th 5 C C ns full speed, see fig. 5 5 C C ns half speed, see fig. 5 sdata release time tsdataz C C 10 ns full speed, see fig. 6 C C 18 ns half speed, see fig. 6 time for data output td C C 10.25 ns full speed, see fig. 7 C C 22 ns half speed, see fig. 7 sdata rise/fall time tsdataotr 2.1 C 6.5 ns full speed, see fig. 7 2.1 C 10 ns half speed, see fig. 7 vio rise time tvio-r 10 C 450 s see fig. 8 vio reset time tvio-rst 10 C C s see fig. 8 reset delay time tsigol 0.12 C C s see fig. 8 figure 4: received clock signal constraints data sheet 12 revision 3.1 - 2016-05-11 v tpma x v tnmin t sclkih t sclkil
BGS15MA12 figure 5: bus active data receiver timing requirements figure 6: bus park cycle timing data sheet 13 revision 3.1 - 2016-05-11 t sd a t az sclk sd a t a v ohmin v olma x bus p ark cy cle signal driv en signal not driv en, pull do wn only t is measur ed fr om sclk v le v el f or a de vice r eceiving sclk and driving sd a t a lines sd a t az tn v tpma x v tnmin v tpma x v tpmin v tpma x v tpmin t s t h t h sclk sd a t a t s
BGS15MA12 figure 7: bus active data transmission timing speci?cation figure 8: requirements for vio-initiated reset data sheet 14 revision 3.1 - 2016-05-11 v ohmin v olma x v tpma x v tpmin t d sclk sd a t a t sd a t a o tr t sd a t a o tr t d t sigol time vio (v) vio ma x vio min v vio-r s t (0.2v) not t o sc ale sclk & sd a t a mus t be held a t lo w le v el fr om deassertion of vio un til the end of t sigol all sla v e r egis t er s se t/r ese t t o manuf actur er ? s de f aults t vio-r s t t vio-r
BGS15MA12 table 10: register mapping register address register name data bits function description default broadcast_id support trigger support r/w 0x0000 register_0 7:0 mode_ctrl switch control 00000000 no yes r/w 0x001d product_id 7:0 product_id this is a read-only register. however, during the programming of the usid a write command sequence is per- formed on this register, even though the write does not change its value. 11010000 no no r 0x001e manufacturer_id 7:0 manufacturer_id [7:0] this is a read-only register. however, during the programming of the usid, a write command sequence is per- formed on this register, even though the write does not change its value. 00011010 no no r 0x001c pm_trig 7:6 pwr_mode 00: normal operation 10 yes no r/w 01: default settings (startup) 10: low power (low power) 11: reserved 5 trigger_mask_2 if this bit is set, trigger 2 is disabled. when all triggers disabled, if writing to a register that is associated to trigger 2, the data goes directly to the desti- nation register. 0 no no 4 trigger_mask_1 if this bit is set, trigger 1 is disabled. when all triggers disabled, if writing to a register that is associated to trigger 1, the data goes directly to the desti- nation register. 0 no no 3 trigger_mask_0 if this bit is set, trigger 0 is disabled. when all triggers disabled, if writing to a register that is associated to trigger 0, the data goes directly to the desti- nation register. 0 no no 2 trigger_2 a write of a one to this bit loads trigger 2s registers. 0 yes no 1 trigger_1 a write of a one to this bit loads trigger 1s registers. 0 yes no r/w 0 trigger_0 a write of a one to this bit loads trigger 0s registers. 0 yes no 0x001f man_usid 7:6 spare these are read-only bits that are re- served and yield a value of 0b00 at readback. 00 no no r/w 5:4 manufacturer_id [9:8] these bits are read-only. however, during the programming of the usid, a write command sequence is per- formed on this register even though the write does not change its value. 01 3:0 usid programmable usid. performing a write to this register using the de- scribed programming sequences will program the usid in devices support- ing this feature. these bits store the usid of the device. usid_sel12 =00 ! 1000, usid_sel12 =01 ! 1001, usid_sel12 =10 ! 1010, usid_sel12 =11 ! 1011 continued on next page data sheet 15 revision 3.1 - 2016-05-11
BGS15MA12 table 10: register mapping C continued from previous page register address register name data bits function description default broadcast_id support trigger support r/w 0x001a rffe_status 7 software reset 0: normal operation 0 no no r/w 1: software reset 6 command_frame_ parity_err command sequence received with parity error - discard command. 0 no no r 5 command_length_err command length error 0 4 address_frame_ parity_err address frame parity error = 1 0 3 data_frame_ parity_err data frame with parity error 0 2 read_unused_reg read command to an invalid address 0 1 write_unused_reg write command to an invalid address 0 0 bid_gid_err read command with a broad- cast_id or group_sid 0 0x001b group_sid 7:4 reserved 0 no no r/w 3:0 group_sid group slave id 0 table 11: modes of operation (truth table, register_0) register_0 bits state mode d7 d6 d5 d4 d3 d2 d1 d0 1 isolation x x x 0 0 0 0 0 2 rx1-ai x x x 0 0 0 0 1 3 rx2-ai x x x 0 0 0 1 0 4 rx3-ai x x x 0 1 0 0 0 5 rx4-ai x x x 0 0 1 0 0 6 rx5-ai x x x 1 0 0 0 0 7 rx1&rx2-ai x x x 0 0 0 1 1 8 rx2&rx3-ai x x x 0 1 0 1 0 9 rx3&rx4-ai x x x 0 1 1 0 0 10 rx4&rx5-ai x x x 1 0 1 0 0 11 rx1&rx3-ai x x x 0 1 0 0 1 12 rx2&rx4-ai x x x 0 0 1 1 0 13 rx3&rx5-ai x x x 1 1 0 0 0 14 rx1&rx4-ai x x x 0 0 1 0 1 15 rx2&rx5-ai x x x 1 0 0 1 0 16 rx1&rx5-ai x x x 1 0 0 0 1 data sheet 16 revision 3.1 - 2016-05-11
BGS15MA12 7 application information pin con?guration and function figure 9: BGS15MA12 pin con?guration (top view) table 12: pin de?nition and function pin no. name function 1 slk mipi rffe clock (input) 2 vio mipi rffe power supply 3 rx5 rf-port rx no. 5 4 rx4 rf-port rx no. 4 5 rx3 rf-port rx no. 3 6 rx2 rf-port rx no. 2 7 rx1 rf-port rx no. 1 8 ssel1 mipi sel port no. 1 (input) 9 ssel2 mipi sel port no. 2 (input) 10 ai rf-input port 11 vbat power supply 12 sdata mipi rffe data (input / output) 13 gnd ground data sheet 17 revision 3.1 - 2016-05-11 1 3 1 1 2 1 1 1 0 9 8 7 6 5 4 3 3 2
BGS15MA12 application board con?guration figure 10: BGS15MA12 application schematic table 13: bill of materials table name value package manufacturer function c1 (optional) 1 nf 0201 various rf bypass 1) c2 (optional) 1 nf 0201 various rf bypass 1) c3 (optional) 1 nf 0201 various rf bypass 1) c4 (optional) 1 nf 0201 various rf bypass 1) n1 BGS15MA12 atslp-12-4 in?neon rf mos switch 1) rf bypass recommended to mitigate power supply noise data sheet 18 revision 3.1 - 2016-05-11 n (p (p (p (p
BGS15MA12 8 package information figure 11: atslp-12-4 package outline (top, side and bottom views) figure 12: marking speci?cation (top view) data sheet 19 revision 3.1 - 2016-05-11 7 8 9 1 2 3 a t s l p - 1 2 - 1 , - 2 , - 3 , - 4 , - 5 , - 7 - p o v 0 3 0 . 0 5 m a x . 0 . 6 p i n 1 m a r k i n g t o p v i e w b o t t o m v i e w 1 . 1 0 . 0 5 0 . 0 5 0 . 2 1 2 x 0 . 0 5 0 . 2 0 . 0 5 1 . 9 0 . 0 5 0 . 2 0 . 0 5 1 2 1 1 1 0 4 5 6 0 . 4 4 x 0 . 4 = 1 . 6 0 . 4 2 x 0 . 4 = 0 . 8 a 0 . 0 5 0 . 7 5 b 1 2 x 0 . 1 b 0 . 1 b 0 . 1 a 0 . 1 a s t a n d o f f a t s l p - 1 2 - 1 , - 2 , - 3 , - 4 , - 5 , - 7 - m k v 0 3 p i n 1 m a r k i n g t y p e c o d e d a t e c o d e ( y w ) 1 2
BGS15MA12 figure 13: footprint recommendation figure 14: atslp-12-4 carrier tape data sheet 20 revision 3.1 - 2016-05-11 0 . 2 5 0 . 2 5 0 . 4 0 . 2 5 0 . 4 0 . 8 0 . 2 5 0 . 2 5 0 . 4 0 . 4 0 . 8 a t s l p - 1 2 - 1 , - 2 , - 3 , - 4 , - 5 , - 7 - f p v 0 1 s t e n c i l a p e r t u r e s c o p p e r s o l d e r m a s k 1 . 3 8 2 . 1 0 . 7 5 a t s l p - 1 2 - 1 , - 2 , - 3 , - 4 , - 5 , - 7 - t p v 0 2 4 p i n 1 m a r k i n g
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